From Clarkdale to Sandy Bridge

The current crop of 32nm "Clarkdale" Cadre i3 and Cadre i5 processors are exclusively dual-core, significant that in order to support 4 threads they must rely on Hyper-Threading. Sandy Bridge on the other hand will offer both dual and quad-core processors, though non all will support Hyper-Threading engineering science.

L3 enshroud support in Clarkdale CPUs was limited to 4MB. The Sandy Bridge architecture differs, though things are a piddling more than confusing. The Core i5 range will provide a 6MB L3 cache, while the Cadre i7 processors volition receive 8MB L3 enshroud. The more affordable Core i3 range will exist cutting down to a 3MB L3 enshroud.

Withal the Sandy Bridge architecture features a shared L3 cache that is shared across all cores and the processor graphics besides. Intel claims that this shared enshroud design delivers more performance and greater energy efficiency.

A problem with the Nehalem architecture was that regardless of how many cores the processor had (two, four or six), each private core had its own individual path to the L3 cache. This makes the processor considerably more complex and becomes a larger upshot when adding more cores. It's said that each core required around 1000 wires and when calculation a GPU to the equation even more wires are required.

Sandy Bridge adds a GPU and video transcoding engine on-die that share the L3 enshroud. Rather than laying out another 2000 wires to the L3 cache Intel introduced a ring bus. The ring features four split up rings: data, request, admit and snoop. Each core, the graphics processor, the video transcoding engine and organization agent all accept their own end on the ring bus.

For those of you who are wondering what the organization amanuensis is, it'south substantially the on-die North Span. Previously Intel has coined this as the un-core, but for some reason it is now titled organisation agent. Regardless everything is much the same in terms of features, as you get a single PCIe ii.0 x16 lane which can be split up into dual x8 lanes when using multi-GPU technology.

The dual-aqueduct DDR3 retentiveness controller has been improved as it falls back on the Lynnfield design. Whereas Clarkdale moved the retention controller off the CPU die and onto the GPU, it is now dorsum on the CPU die with the Sandy Span architecture.

Another major modify has to exercise with the DMI interface betwixt the processor and the Platform Controller Hub (PCH) otherwise known equally the chipset. The LGA1156 processors communicate to the PCH using the DMI interface which provides a bandwidth of 2GB/s. Considering the PCI Express 2.0 x16 lanes and the DDR3 DIMM slots are connected directly to the processor, the limited 2GB/southward bandwidth was never a trouble.

However with the introduction of SATA 6Gb/s and USB iii.0, more than bandwidth between the CPU and PCH will be required. Therefore Intel has upgraded to the DMI ii interface, which provides four PCI Limited two.0 x1 lanes for a maximum theoretical bandwidth of 2GB/south in each direction, for an aggregate of 4GB/s.

Too new to Sandy Span is the Intel Avant-garde Vector Extensions (AVX) which is the latest expansion of the Intel instruction set. It extends the Intel Streaming SIMD Extensions (SSE) from 128-bit vectors into 256-fleck vectors. Intel AVX addresses the connected demand for vector floating-signal performance in mainstream scientific and engineering numerical applications, visual processing, recognition, information-mining/synthesis, gaming, physics, cryptography and other areas of applications.

The enhancement in Intel AVX allows for improved operation due to wider vectors, new extensible syntax, and rich functionality including the ability to ameliorate manage, rearrange, and sort data.